The present invention relates to a memory system, a semiconductor memory device and a method of driving the semiconductor memory device.
High integration is required for semiconductor memory for reasons of the enlargement of memory capacity due to a reduction in their unit price per bit.
As a technique to break through the limits of a device's high integration by miniaturization on the two-dimensional plane of a silicon substrate, there is known a method of forming the device into a three-dimensional structure by stacking transistors.
However, simply processing and stacking layers of transistors, one layer at a time, involves an increase in the number of lithography processes for patterning the structure of transistors as the number of layers increases, thereby resulting in an cost increase.
As a method wherein the number of lithography processes required for patterning is independent of the number of laminations, there is a collectively-processed lamination method. In this method, lower select transistors are first formed on a silicon substrate.
Next, polysilicon layers and silicon dioxide films are alternately stacked on top of each other over the lower select transistors. The number of polysilicon layers is determined according to the number of transistors in a memory structure wherein the transistors are stacked in a direction perpendicular to the silicon substrate.
Next, holes penetrating to the drain diffused layers of the lower select transistors are formed and charge-accumulating layers are formed on the side walls of the holes. Since the transistors of a memory region are collectively formed by creating holes, the number of lithography processes does not increase even if the number of laminations is increased. After amorphous silicon to serve as silicon bodies is deposited in the holes and word lines are processed, upper select transistors are formed in the memory region (having a polysilicon-silicon dioxide film laminated structure).
Now, the operating principles of a lamination-structured memory formed in such a manner as described above will be described. When writing data, an off level, i.e., 0 V, is applied to the gates of the lower select transistors (lower select gates), a voltage Vsg is applied to the upper select gates of selected lines, and an off level (0 V) is applied to the upper select gates of unselected lines.
When writing data 0, bit lines are set to 0 V, word lines corresponding to cells to be written with data 0 are boosted to Vprog, and all other word lines are boosted to Vpass. Vprog is assumed to be sufficiently higher than a voltage required to inject electrons into the charge-accumulating layers.
Since the upper select transistors are in an on state, the silicon bodies are maintained at 0 V, i.e., a bit line potential, and data 0 is written to the cells to be written with data 0 by the application of Vprog which is a word line level.
When writing data 1, the bit lines are set to voltage Vdd, word lines corresponding to cells to be written with data 1 are boosted to Vprog, and all other word lines are boosted to Vpass. The potential Vbody of the silicon bodies is raised by the coupling of the word lines boosted to Vpass, the upper select transistors go into an off state due to a back gate effect, and the silicon body potential Vbody is thus maintained.
By controlling Vpass, the boost rate thereof, and the value of the gate potential level Vsg of the upper select transistors, it is possible to control the value of Vbody. Control needs to be performed so that Vprog−Vbody is sufficiently smaller than a potential required to inject electrons into the charge-accumulating layers.
When erasing data, the word lines of a block to be erased are boosted to 0 V and the bit lines and source lines or the P wells thereof are boosted to the erase potential Verase. The potential Vsg of select gates is set to a potential value that satisfies Verase>Vsg. The silicon body potential Vbody is raised by a hole current generated by band-to-band tunneling due to a potential difference between the select gates and the source lines or bit lines, thereby erasing data.
The difference between the erase potential Verase and the select gate potential Vsg needs to be maintained so as to be able to generate a sufficient amount of hole current.
When reading data, the source lines are set to 0 V, the lower select gates are set to Vdd, i.e., an on level, word lines corresponding to cells to be read are set to 0 V, word lines corresponding to cells to be not read are set to Vread, the upper select gates are set to Vdd, and bit lines are set to Vbl.
If electrons are accumulated in the charge-accumulating layers, the threshold is 0 V or higher and, therefore, the bit line potential Vbl is maintained. On the other hand, if holes are accumulated in the charge-accumulating layers, the bit line potential Vbl is equalized to the potential of the source lines and is, therefore, lowered since the threshold is lower than 0 V and the cells to be read go into an on state.
As a result, it is possible to derive the state of charges accumulated in the charge-accumulating layers as a signal. Note that a voltage adequate for the cells being not read to turn on is selected for Vread.
When writing data 1, the source voltage of the lower select transistors is set to 0 V, the drain voltage thereof is set to Vbody, and the gate voltage thereof is set to 0 V. Holes generated by band-to-band tunneling at drain ends are accumulated on gate surfaces due to gate electric fields and, therefore, the gate electric fields are shielded. As a result, there is the possibility that it is no longer possible to maintain depleted regions in the central parts of the silicon bodies, thereby causing a leak current to flow.
Thus, the memory device has the problem that if the leak current cannot be kept sufficiently low, the silicon body potential Vbody drops and there occurs miswriting wherein data 0 is written to cells to which data 1 should be written.
On the other hand, in order to boost the silicon bodies at the time of erase operation by boosting the bit lines and source lines (or P wells), there is the need for a hole current to be generated by band-to-band tunneling at an overlapping portion between each select gate and each diffused layer on the silicon body side.
If the hole current is not sufficiently large, it is not possible to boost the silicon bodies by the bit line and source line potentials.
As described above, in the case of the lamination-structure memory formed using a collectively-processed lamination method, it is necessary to suppress band-to-band tunneling at the time of write operation and accelerate the tunneling at the time of erase operation.